1. Field of the Invention
The present invention relates to a class-D amplifier, and more particular relates to a technique for improving the resolution of an output signal.
2. Description of Related Art
With progressive development toward processing digital audio signals, more and more signal sources have been digitized, and thus class-D amplifiers featuring full digital processing are gradually prevailing.
FIG. 1 is a schematic view illustrating a conventional half-bridge class-D amplifier. Referring to FIG. 1, a class-D amplifier 10 includes a controlling logic circuit 20 and an output module 30. The class-D amplifier 10 modulates an input signal Sin+ to a pulse width modulation (PWM) signal PWM1 through employing a switching technology of the output module 30. Conventionally, a power supply 40 is only capable of providing a constant voltage VDD. The output module 30 is coupled to the constant voltage VDD and a ground terminal GND. Switches 101 and 102 generate the two-level PWM signal PWM1 while the switches 101 and 102 are completely turned on or turned off.
Next, an additionally disposed low-pass filter 50 is utilized for filtering out high-band noises caused by the PWM signal PWM1 when the output module 30 is switched on or off. Finally, a direct current (DC) filter capacitor 60 is employed to remove unwanted DC noises of the PWM signal PWM1, so as to drive a speaker 110.
FIG. 2 is a schematic view illustrating a waveform of a PWM signal generated by the class-D amplifier depicted in FIG. 1. Referring to FIGS. 1 and 2, the input signal Sin+ is assumed to have a signed 2's complement value. A triangular waveform 120 is provided by a controlling logic circuit 20 and is represented by the signed 2's complement value as well. The controlling logic circuit 20 is able to compare the input signal Sin+ with the triangular waveform 120, and thereby controlling signals SC1 and SC2 are generated. The controlling signals SC1 and SC2 determine whether the switches 101 and 102 are turned on, so as to generate the PWM signal PWM1.
In particular, as the amplitude of the input signal Sin+ is greater than the amplitude of the triangular waveform 120, the PWM signal PWM1 reaches a high voltage level, i.e. the voltage VDD. By contrast, as the amplitude of the input signal Sin+ is less than the amplitude of the triangular waveform 120, a low voltage level, i.e. the voltage GND, is provided to the PWM signal PWM1.
Note that a reference clock is required for generating all kinds of signals. In other words, resolution 130 represented by the PWM signal PWM1 depicted in FIG. 1 is restricted by frequencies of the clock of the class-D amplifier 10. Hence, certain quantization errors are generated by the PWM signal PWM1, further posing an impact on a signal to noise ratio (SNR) or a dynamic range (DR) of the class-D amplifier 10.
To increase the resolution of the PWM signal, a full-bridge class-D amplifier for increasing level variations of the PWM signal is proposed by the pertinent art. FIG. 3 is a schematic view illustrating a conventional full-bridge class-D amplifier. FIG. 4 is a schematic view illustrating a waveform of the PWM signal generated by the class-D amplifier depicted in FIG. 3. Referring to FIGS. 3 and 4, an output module 31 of a full-bridge class-D amplifier 11 includes not only the switches 101 and 102 but also switches 103 and 104. The class-D amplifier 11 is not only able to generate the PWM signal PWM1 in the manner indicated hereinbefore, but also capable of generating another PWM signal PWM2 with use of a controlling logic circuit 21 and the switches 103 and 104, which is elaborated below.
A 180-degree phase shifting of the input signal Sin+ is first performed by the controlling logic circuit 21 for generating the input signal Sin−. Next, the input signal Sin− is compared with the triangular waveform 120, such that controlling signals SC3 and SC4 are generated for determining whether the switches 103 and 104 are turned on or not. Thereby, the PWM signal PWM2 is generated.
In particular, as the amplitude of the input signal Sin− is greater than the amplitude of the triangular waveform 120, the PWM signal PWM2 reaches the high voltage level, i.e. the voltage VDD. By contrast, as the amplitude of the input signal Sin− is less than the amplitude of the triangular waveform 120, the PWM signal PWM2 is set to the low voltage level, i.e. the voltage GND.
The PWM signals PWM1 and PWM2 respectively connect two ends of the speaker. Thus, a signal received by the speaker 110 can be considered as a PWM signal PWM3 calculated by subtracting the PWM signals PWM1 and PWM2, whereby the PWM signal PWM3 generated by the class-D amplifier 11 is provided with three levels, i.e. the voltages VDD, 0, and −VDD. As such, the relatively great SNR can be achieved by the class-D amplifier 11.